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| author | Anhgelus Morhtuuzh <william@herges.fr> | 2026-01-20 13:55:21 +0100 |
|---|---|---|
| committer | Anhgelus Morhtuuzh <william@herges.fr> | 2026-01-20 13:55:21 +0100 |
| commit | 42e9569176360b5e1881d317c74ce8522a2af6d1 (patch) | |
| tree | 9df17cba32ac37cf34f486f3fbf335a19f8a14ca /semestre 3/architecture des ordinateurs/td/25-12-10.md | |
| parent | ecf05510045b2ac78b479ae746a43078e22cee4f (diff) | |
Derniers cours du S3
Diffstat (limited to 'semestre 3/architecture des ordinateurs/td/25-12-10.md')
| -rw-r--r-- | semestre 3/architecture des ordinateurs/td/25-12-10.md | 51 |
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diff --git a/semestre 3/architecture des ordinateurs/td/25-12-10.md b/semestre 3/architecture des ordinateurs/td/25-12-10.md new file mode 100644 index 0000000..26df476 --- /dev/null +++ b/semestre 3/architecture des ordinateurs/td/25-12-10.md @@ -0,0 +1,51 @@ +--- +tags: + - sorbonne + - informatique + - architecture-des-ordinateurs + - td +semestre: 3 +--- +Un transfert est le déplacement d'une donnée lors d'un cycle + +`LO <- HI or 0` + +`r6 <- r4 or 0` + +`AD <- PC + AD` + +``` +AD <- r[20] +r[8] <- AD + r[18] +``` + +``` +AD <- r[8] +AD <- m[AD] +``` + +``` +IR <- m[PC] +PC <- PC + 4 +AD <- r[5] or 0 +r[3] <- r[7] + AD +``` + +``` +IR <- m[PC] +PC <- PC + 4 +AD <- r[8] + 4 +DT <- m[AD] +r[4] <- DT or 0 +``` + +``` +IR <- m[PC] +PC <- PC + 4 +AD <- r[6] or 0 +m[AD] <- r[9] or 0 +``` + +1. `add $9, $6, $8` +2. `sw $9, 12($10)` +3. `jalr $9, $6` |