Derniers cours du S3

7 files changed, 1078 insertions, 17 deletions

diff --git a/semestre 3/architecture des ordinateurs/1- Représentation de l'information.md b/semestre 3/architecture des ordinateurs/1- Représentation de l'information.md
index 6d6d266..bfab1c4 100644
--- a/semestre 3/architecture des ordinateurs/1- Représentation de l'information.md
+++ b/semestre 3/architecture des ordinateurs/1- Représentation de l'information.md
@@ -105,11 +105,11 @@ Toute fonction booléenne peut être décrite par une composition des fonctions
 Soit $A$ un mot binaire de $n$ bits avec la famille $(a_i)_{i\in[0,n-1]}$ qui forme les bits de $A$.
 Si $p > n-1$, on a que $[p,n-1] = \varnothing$ par abus de langage
 
-$B = A << p$ tel que 
+$B = A \ll p$ tel que 
 |> $\forall i\in[0,p-1], b_i = 0$
 |> $\forall i\in[p,n-1], b_i = a_{i-p}$
 
-$B = A >> p$ tel que
+$B = A \gg p$ tel que
 |> $\forall i\in[0,p-1], b_i = a_{i+p}$
 |> $\forall i\in[p,n-1], b_i = 0$
 
@@ -119,7 +119,7 @@ $B = A >> p$ tel que
 > Si $A = 0101$ et qu'on souhaite avoir $10$, on fait $m = 0110$
 > |> $A+m = 0100$
 > Puis on décale de 1 pour supprimer la valeur inutile
-> |> $A >> 1 = 0010$
+> |> $A \gg 1 = 0010$
 
 > [!warning] Comment faire un bon mask ?
 > Toujours ne mettre que des 1 là où on veut garder des valeurs, sinon on risque de perdre des infos !
@@ -254,8 +254,8 @@ Attention à l'overflow !
 |> la retenu est ignorée quand on dépasse -> est de l'arithmétique modulaire sur $2^n$
 
 Décaler à gauche de $n$ revient à multiplier par la base $B^n$ 
-|> $(a_{p-1}\ldots a_0)_b\times 2^n = (a_{p-1}\ldots a_0)_b << n = (a_{p-1}\ldots a_0\underbrace{0\ldots0}_n)_b$
-|> $(a_{p-1}\ldots a_0)_b/2^n = (a_{p-1}\ldots a_0)_b >> n = (a_{p-1}\ldots a_{n})$
+|> $(a_{p-1}\ldots a_0)_b\times 2^n = (a_{p-1}\ldots a_0)_b \ll n = (a_{p-1}\ldots a_0\underbrace{0\ldots0}_n)_b$
+|> $(a_{p-1}\ldots a_0)_b/2^n = (a_{p-1}\ldots a_0)_b \gg n = (a_{p-1}\ldots a_{n})$
 ## Entiers relatifs
 On les appelle les nombre entiers signés
 
diff --git a/semestre 3/architecture des ordinateurs/2- Programmation en ASM Mips.md b/semestre 3/architecture des ordinateurs/2- Programmation en ASM Mips.md
index edc5cd3..568a612 100644
--- a/semestre 3/architecture des ordinateurs/2- Programmation en ASM Mips.md
+++ b/semestre 3/architecture des ordinateurs/2- Programmation en ASM Mips.md
@@ -395,22 +395,22 @@ int main(){
 ```asm
 .text
 # prologue
-addiu $29, $29, -12 # car on stock 3 mots
+	addiu $29, $29, -12 # car on stock 3 mots
 # initialisation des variables
-ori $8, $0, 1
-sw $8, 0($29)
-ori $8, $0, 2
-sw $8, 4($29)
+	ori $8, $0, 1
+	sw $8, 0($29)
+	ori $8, $0, 2
+	sw $8, 4($29)
 # corps du main
-lw $8, 0($29)
-lw $9, 4($29)
-addu $8, $8, $9
-sw $9, 8($29)
+	lw $8, 0($29)
+	lw $9, 4($29)
+	addu $8, $8, $9
+	sw $9, 8($29)
 # épilogue
-addiu $29, $29, 12
+	addiu $29, $29, 12
 # exit
-ori $2, $0, 10
-syscall
+	ori $2, $0, 10
+	syscall
 ```
 ## Fonction
 Pour arriver à une fonction, on utilise `jal label`
diff --git a/semestre 3/architecture des ordinateurs/td/25-11-26.md b/semestre 3/architecture des ordinateurs/td/25-11-26.md
index e72f90a..47555b1 100644
--- a/semestre 3/architecture des ordinateurs/td/25-11-26.md
+++ b/semestre 3/architecture des ordinateurs/td/25-11-26.md
@@ -73,6 +73,10 @@ $(\bar a.b.c)+(a.\bar b.\bar c)+(a.b.\bar c)+(a.b.c)$
 | 1     | 1     | 0        | 0   | 1         |
 $s=(\bar u_1.\bar u_2.c_{in})+(\bar u_1.u_2.\bar c_{in})+(u_1.\bar u_2.\bar c_{in})+(u_1.u_2.c_{in})=u_1\oplus u_2\oplus c_{in}$ où $\oplus$ est $\mathrm{xor}$ (à refaire)
 $c_{out}=(\bar u_1.u_2.c_{in})+(u_1.\bar u_2.c_{in})+(u_1.u_2.c_{in})+(u_1.u_2.\bar c_{in})=a.b+a.c_{in}+b.c_{in}=c_{in}.(a\oplus b)+a.b$ (à refaire)
+
+$s = (\bar a . \bar b . c)+(\bar a.b.\bar c)+(a.\bar b.\bar c)+(a.b.c)$
+$s = (\bar a . (\bar b + (\bar a.b.\bar c)) . c + (\bar a.b.\bar c))$
+
 | $i_3$ | $i_2$ | $i_1$ | $i_0$ | $a$ | $b$ | $c$ | $d$ | $e$ | $f$ | $g$ |
 | ----- | ----- | ----- | ----- | --- | --- | --- | --- | --- | --- | --- |
 | 0     | 0     | 0     | 0     | 1   | 1   | 1   | 1   | 1   | 1   |     |
diff --git a/semestre 3/architecture des ordinateurs/td/25-12-10.md b/semestre 3/architecture des ordinateurs/td/25-12-10.md
new file mode 100644
index 0000000..26df476
--- /dev/null
+++ b/semestre 3/architecture des ordinateurs/td/25-12-10.md
@@ -0,0 +1,51 @@
+---
+tags:
+  - sorbonne
+  - informatique
+  - architecture-des-ordinateurs
+  - td
+semestre: 3
+---
+Un transfert est le déplacement d'une donnée lors d'un cycle
+
+`LO <- HI or 0`
+
+`r6 <- r4 or 0`
+
+`AD <- PC + AD`
+
+```
+AD <- r[20]
+r[8] <- AD + r[18]
+```
+
+```
+AD <- r[8]
+AD <- m[AD]
+```
+
+```
+IR <- m[PC]
+PC <- PC + 4
+AD <- r[5] or 0
+r[3] <- r[7] + AD
+```
+
+```
+IR <- m[PC]
+PC <- PC + 4
+AD <- r[8] + 4
+DT <- m[AD]
+r[4] <- DT or 0
+```
+
+```
+IR <- m[PC]
+PC <- PC + 4
+AD <- r[6] or 0
+m[AD] <- r[9] or 0
+```
+
+1. `add $9, $6, $8`
+2. `sw $9, 12($10)`
+3. `jalr $9, $6`
diff --git a/semestre 3/architecture des ordinateurs/td/25-12-17.md b/semestre 3/architecture des ordinateurs/td/25-12-17.md
new file mode 100644
index 0000000..f2db8c5
--- /dev/null
+++ b/semestre 3/architecture des ordinateurs/td/25-12-17.md
@@ -0,0 +1,95 @@
+---
+tags:
+  - informatique
+  - sorbonne
+  - td
+  - architecture-des-ordinateurs
+Semestre: 3
+---
+4 états -> 2 bits
+4 + 3 = 7 transitions
+|> 0 -> 1, 1 -> 2, 2 -> 3, 3 -> 0, 1 -> 0, 2 -> 0, 0 -> 0
+
+RST = reset
+
+$F_1 = \overline{\text{RST}} . (c_1 \oplus c_2)$
+$F_0 = \overline{\text{RST}} . \bar c_0$
+
+```mermaid
+flowchart LR
+	A-- 1 ---A
+	A-- 0 ---B
+	B-- 0 ---B
+	B-- 1 ---C
+	C-- 1 ---A
+	C-- 0 ---D
+	D-- 0 ---B
+	D-- 1 ---E
+	E-- 0,1 ---E
+```
+
+```mermaid
+flowchart LR
+	A-- 0 ---B
+	B-- 1 ---C
+	C-- 0 ---D
+	D-- 1 ---E
+```
+
+5 états -> 3 bits
+4 transitions
+
+| États | $C_2$ | $C_1$ | $C_0$ |
+| ----- | ----- | ----- | ----- |
+| A     | 0     | 0     | 0     |
+| B     | 0     | 0     | 1     |
+| C     | 0     | 1     | 0     |
+| D     | 0     | 1     | 1     |
+| E     | 1     | 0     | 0     |
+
+ext_A = ext_B = ext_C
+WE_A = WE_B = WE_C
+ext_D = 0
+
+ADD = 0
+1. `RA,RB,RC` -> ext_{A,B,C}+WE_{A,B,C}
+2. `RD = RA+RB` -> OP_A+OP_B + ADD + WE_D
+3. `RD = RD + RC`
+
+5 états -> 3 bits
+6 transitions
+
+init = chargement dans les registres
+s0 = comparaison
+s1 = a < b -> a = a, b = b-a
+s2 = a > b -> a = a-b, b = a
+end = a == b -> met le résultat dans le registre
+
+| États | Valeur |
+| ----- | ------ |
+| init  | 0      |
+| $S_0$ | 1      |
+| $S_1$ | 10     |
+| $S_2$ | 11     |
+| end   | 100    |
+
+| $C_2$ | $C_1$ | $C_0$ | $a>b$ | $a=b$ | $F_2$ | $F_1$ | $F_0$ |
+| ----- | ----- | ----- | ----- | ----- | ----- | ----- | ----- |
+| 0     | 0     | 0     | 0     | 0     | 0     | 0     | 1     |
+| 0     | 0     | 0     | 0     | 1     | 0     | 0     | 1     |
+| 0     | 0     | 0     | 1     | 0     | 0     | 0     | 1     |
+| 0     | 0     | 1     | 0     | 0     | 0     | 1     | 0     |
+| 0     | 0     | 1     | 0     | 1     | 1     | 0     | 0     |
+| 0     | 0     | 1     | 1     | 0     | 0     | 1     | 1     |
+| 0     | 1     | 0     | 0     | 0     | 0     | 0     | 1     |
+| 0     | 1     | 0     | 0     | 1     | 0     | 0     | 1     |
+| 0     | 1     | 0     | 1     | 0     | 0     | 0     | 1     |
+| 0     | 1     | 1     | 0     | 0     | 0     | 0     | 1     |
+| 0     | 1     | 1     | 0     | 1     | 0     | 0     | 1     |
+| 0     | 1     | 1     | 1     | 0     | 0     | 0     | 1     |
+| 1     | 0     | 0     | 0     | 0     | 1     | 0     | 0     |
+| 1     | 0     | 0     | 0     | 1     | 1     | 0     | 0     |
+| 1     | 0     | 0     | 1     | 0     | 1     | 0     | 0     |
+$F_0 = \overline{S_0.((a<b)+(a=b))+end}$
+$F_1=S_0.(\overline{a=b})$
+$F_2 = end+S_0.(a=b)$
diff --git a/semestre 3/architecture des ordinateurs/tme/tme10/TP10_CheminDonneesMarep.circ b/semestre 3/architecture des ordinateurs/tme/tme10/TP10_CheminDonneesMarep.circ
new file mode 100644
index 0000000..fd05829
--- /dev/null
+++ b/semestre 3/architecture des ordinateurs/tme/tme10/TP10_CheminDonneesMarep.circ
@@ -0,0 +1,567 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<project source="4.0.0" version="1.0">
+  This file is intended to be loaded by Logisim-evolution v4.0.0(https://github.com/logisim-evolution/).
+
+  <lib desc="#Wiring" name="0">
+    <tool name="Splitter">
+      <a name="facing" val="west"/>
+    </tool>
+    <tool name="Pin">
+      <a name="appearance" val="classic"/>
+    </tool>
+    <tool name="Probe">
+      <a name="appearance" val="classic"/>
+      <a name="facing" val="west"/>
+    </tool>
+    <tool name="Tunnel">
+      <a name="width" val="3"/>
+    </tool>
+    <tool name="Clock">
+      <a name="appearance" val="classic"/>
+      <a name="facing" val="south"/>
+    </tool>
+    <tool name="Constant">
+      <a name="facing" val="south"/>
+      <a name="value" val="0xf"/>
+      <a name="width" val="4"/>
+    </tool>
+  </lib>
+  <lib desc="#Gates" name="1"/>
+  <lib desc="#Plexers" name="2">
+    <tool name="Demultiplexer">
+      <a name="enable" val="true"/>
+      <a name="select" val="2"/>
+    </tool>
+  </lib>
+  <lib desc="#Arithmetic" name="3"/>
+  <lib desc="#Memory" name="4"/>
+  <lib desc="#I/O" name="5"/>
+  <lib desc="#Base" name="6">
+    <tool name="Text Tool">
+      <a name="font" val="SansSerif plain 12"/>
+    </tool>
+  </lib>
+  <main name="main"/>
+  <options>
+    <a name="gateUndefined" val="ignore"/>
+    <a name="simlimit" val="1000"/>
+    <a name="simrand" val="0"/>
+  </options>
+  <mappings>
+    <tool lib="6" map="Button2" name="Menu Tool"/>
+    <tool lib="6" map="Button3" name="Menu Tool"/>
+    <tool lib="6" map="Ctrl Button1" name="Menu Tool"/>
+  </mappings>
+  <toolbar>
+    <tool lib="6" name="Poke Tool"/>
+    <tool lib="6" name="Edit Tool"/>
+    <tool lib="6" name="Text Tool">
+      <a name="font" val="SansSerif plain 12"/>
+    </tool>
+    <sep/>
+    <tool lib="0" name="Pin"/>
+    <tool lib="0" name="Pin">
+      <a name="facing" val="west"/>
+      <a name="labelloc" val="east"/>
+      <a name="type" val="output"/>
+    </tool>
+    <tool lib="1" name="NOT Gate"/>
+    <tool lib="1" name="AND Gate"/>
+    <tool lib="1" name="OR Gate"/>
+  </toolbar>
+  <circuit name="main">
+    <a name="circuit" val="main"/>
+    <a name="clabelfont" val="SansSerif plain 12"/>
+    <a name="simulationFrequency" val="1.0"/>
+    <comp lib="0" loc="(1000,720)" name="Pin">
+      <a name="appearance" val="classic"/>
+      <a name="facing" val="north"/>
+      <a name="label" val="StoreCommand"/>
+    </comp>
+    <comp lib="0" loc="(1040,380)" name="Pin">
+      <a name="appearance" val="classic"/>
+      <a name="facing" val="west"/>
+      <a name="label" val="ValeurSurResOut_DataOut_a56fa60d"/>
+      <a name="labelloc" val="south"/>
+      <a name="type" val="output"/>
+      <a name="width" val="4"/>
+    </comp>
+    <comp lib="0" loc="(110,670)" name="Pin">
+      <a name="appearance" val="classic"/>
+    </comp>
+    <comp lib="0" loc="(1110,620)" name="Constant">
+      <a name="facing" val="north"/>
+    </comp>
+    <comp lib="0" loc="(1130,150)" name="Pin">
+      <a name="appearance" val="classic"/>
+      <a name="facing" val="south"/>
+      <a name="label" val="ValeurSurDataIn"/>
+      <a name="labelloc" val="north"/>
+      <a name="type" val="output"/>
+      <a name="width" val="4"/>
+    </comp>
+    <comp lib="0" loc="(1150,700)" name="Pin">
+      <a name="appearance" val="classic"/>
+      <a name="facing" val="north"/>
+      <a name="label" val="LoadCommand"/>
+      <a name="labelloc" val="east"/>
+    </comp>
+    <comp lib="0" loc="(160,300)" name="Pin">
+      <a name="appearance" val="classic"/>
+      <a name="label" val="Constante"/>
+      <a name="width" val="4"/>
+    </comp>
+    <comp lib="0" loc="(230,580)" name="Pin">
+      <a name="appearance" val="classic"/>
+      <a name="facing" val="north"/>
+      <a name="label" val="CteOutputYEnable"/>
+    </comp>
+    <comp lib="0" loc="(270,40)" name="Pin">
+      <a name="appearance" val="classic"/>
+      <a name="facing" val="south"/>
+      <a name="label" val="CteOutputXEnable"/>
+      <a name="labelloc" val="north"/>
+    </comp>
+    <comp lib="0" loc="(360,440)" name="Pin">
+      <a name="appearance" val="classic"/>
+      <a name="facing" val="south"/>
+      <a name="label" val="ValeurSurBusY"/>
+      <a name="labelloc" val="north"/>
+      <a name="type" val="output"/>
+      <a name="width" val="4"/>
+    </comp>
+    <comp lib="0" loc="(370,200)" name="Pin">
+      <a name="appearance" val="classic"/>
+      <a name="facing" val="south"/>
+      <a name="label" val="ValeurSurBusX"/>
+      <a name="labelloc" val="north"/>
+      <a name="type" val="output"/>
+      <a name="width" val="4"/>
+    </comp>
+    <comp lib="0" loc="(440,120)" name="Pin">
+      <a name="appearance" val="classic"/>
+      <a name="label" val="NumRegToWrite"/>
+      <a name="width" val="2"/>
+    </comp>
+    <comp lib="0" loc="(440,90)" name="Pin">
+      <a name="appearance" val="classic"/>
+      <a name="label" val="NumRegToRead"/>
+      <a name="width" val="2"/>
+    </comp>
+    <comp lib="0" loc="(460,60)" name="Pin">
+      <a name="appearance" val="classic"/>
+      <a name="facing" val="south"/>
+      <a name="label" val="RegWriteEnable"/>
+      <a name="labelloc" val="north"/>
+    </comp>
+    <comp lib="0" loc="(550,40)" name="Pin">
+      <a name="appearance" val="classic"/>
+      <a name="facing" val="south"/>
+      <a name="label" val="RegOutputXEnable"/>
+      <a name="labelloc" val="north"/>
+    </comp>
+    <comp lib="0" loc="(570,390)" name="Constant">
+      <a name="value" val="0x0"/>
+    </comp>
+    <comp lib="0" loc="(590,560)" name="Pin">
+      <a name="appearance" val="classic"/>
+      <a name="facing" val="north"/>
+      <a name="label" val="ADOutputYEnable"/>
+    </comp>
+    <comp lib="0" loc="(600,100)" name="Pin">
+      <a name="appearance" val="classic"/>
+      <a name="facing" val="south"/>
+      <a name="label" val="ADWriteEnable"/>
+      <a name="labelloc" val="north"/>
+    </comp>
+    <comp lib="0" loc="(660,50)" name="Pin">
+      <a name="appearance" val="classic"/>
+      <a name="facing" val="south"/>
+      <a name="label" val="ADOutputXEnable"/>
+      <a name="labelloc" val="north"/>
+    </comp>
+    <comp lib="0" loc="(680,620)" name="Pin">
+      <a name="appearance" val="classic"/>
+      <a name="facing" val="north"/>
+      <a name="label" val="ADOutputAddressEnable"/>
+      <a name="labelloc" val="east"/>
+    </comp>
+    <comp lib="0" loc="(730,90)" name="Pin">
+      <a name="appearance" val="classic"/>
+      <a name="facing" val="south"/>
+      <a name="label" val="DTWriteEnable"/>
+      <a name="labelloc" val="north"/>
+    </comp>
+    <comp lib="0" loc="(790,40)" name="Pin">
+      <a name="appearance" val="classic"/>
+      <a name="facing" val="south"/>
+      <a name="label" val="DTOutputXEnable"/>
+      <a name="labelloc" val="north"/>
+    </comp>
+    <comp lib="0" loc="(790,600)" name="Pin">
+      <a name="appearance" val="classic"/>
+      <a name="facing" val="north"/>
+      <a name="label" val="DTOutputYEnable"/>
+      <a name="labelloc" val="east"/>
+    </comp>
+    <comp lib="0" loc="(890,540)" name="Pin">
+      <a name="appearance" val="classic"/>
+      <a name="facing" val="south"/>
+      <a name="label" val="ValeurSurBusAddress"/>
+      <a name="labelloc" val="north"/>
+      <a name="type" val="output"/>
+      <a name="width" val="4"/>
+    </comp>
+    <comp lib="0" loc="(940,310)" name="Constant">
+      <a name="facing" val="south"/>
+      <a name="value" val="0x0"/>
+    </comp>
+    <comp lib="1" loc="(250,230)" name="Controlled Buffer">
+      <a name="facing" val="north"/>
+      <a name="width" val="4"/>
+    </comp>
+    <comp lib="1" loc="(250,450)" name="Controlled Buffer">
+      <a name="facing" val="south"/>
+      <a name="width" val="4"/>
+    </comp>
+    <comp lib="1" loc="(510,260)" name="Controlled Buffer">
+      <a name="facing" val="south"/>
+      <a name="width" val="4"/>
+    </comp>
+    <comp lib="1" loc="(540,230)" name="Controlled Buffer">
+      <a name="facing" val="north"/>
+      <a name="width" val="4"/>
+    </comp>
+    <comp lib="1" loc="(640,220)" name="Controlled Buffer">
+      <a name="facing" val="north"/>
+      <a name="width" val="4"/>
+    </comp>
+    <comp lib="1" loc="(660,440)" name="Controlled Buffer">
+      <a name="facing" val="south"/>
+      <a name="width" val="4"/>
+    </comp>
+    <comp lib="1" loc="(700,440)" name="Controlled Buffer">
+      <a name="facing" val="south"/>
+      <a name="width" val="4"/>
+    </comp>
+    <comp lib="1" loc="(830,220)" name="Controlled Buffer">
+      <a name="facing" val="north"/>
+      <a name="width" val="4"/>
+    </comp>
+    <comp lib="1" loc="(830,440)" name="Controlled Buffer">
+      <a name="facing" val="south"/>
+      <a name="width" val="4"/>
+    </comp>
+    <comp lib="3" loc="(960,340)" name="Adder">
+      <a name="width" val="4"/>
+    </comp>
+    <comp lib="4" loc="(1260,520)" name="RAM">
+      <a name="addrWidth" val="4"/>
+      <a name="appearance" val="logisim_evolution"/>
+      <a name="dataWidth" val="4"/>
+      <a name="labelfont" val="SansSerif bold 12"/>
+    </comp>
+    <comp lib="4" loc="(630,280)" name="Register">
+      <a name="appearance" val="logisim_evolution"/>
+      <a name="width" val="4"/>
+    </comp>
+    <comp lib="4" loc="(750,270)" name="Register">
+      <a name="appearance" val="logisim_evolution"/>
+      <a name="width" val="4"/>
+    </comp>
+    <comp lib="6" loc="(120,660)" name="Text">
+      <a name="text" val="clock"/>
+    </comp>
+    <comp lib="6" loc="(130,280)" name="Text">
+      <a name="text" val="bloc de constantes 4 bits"/>
+    </comp>
+    <comp lib="6" loc="(305,200)" name="Text">
+      <a name="text" val="bus X"/>
+    </comp>
+    <comp lib="6" loc="(305,440)" name="Text">
+      <a name="text" val="bus Y"/>
+    </comp>
+    <comp lib="6" loc="(440,340)" name="Text">
+      <a name="text" val="banc de 4 registres"/>
+    </comp>
+    <comp lib="6" loc="(440,355)" name="Text">
+      <a name="text" val="4 bits"/>
+    </comp>
+    <comp lib="6" loc="(785,555)" name="Text">
+      <a name="text" val="bus ADRESSE"/>
+    </comp>
+    <comp lib="6" loc="(885,185)" name="Text">
+      <a name="text" val="RES_OUT"/>
+    </comp>
+    <comp lib="6" loc="(940,150)" name="Text">
+      <a name="text" val="DATA_IN"/>
+    </comp>
+    <comp lib="6" loc="(940,380)" name="Text">
+      <a name="text" val="ADD"/>
+    </comp>
+    <comp loc="(530,310)" name="banc_registre">
+      <a name="labelloc" val="south"/>
+    </comp>
+    <wire from="(1000,710)" to="(1000,720)"/>
+    <wire from="(1000,710)" to="(1090,710)"/>
+    <wire from="(1020,190)" to="(1020,340)"/>
+    <wire from="(1020,340)" to="(1020,380)"/>
+    <wire from="(1020,380)" to="(1020,610)"/>
+    <wire from="(1020,380)" to="(1040,380)"/>
+    <wire from="(1020,610)" to="(1260,610)"/>
+    <wire from="(1090,570)" to="(1090,710)"/>
+    <wire from="(1090,570)" to="(1260,570)"/>
+    <wire from="(110,670)" to="(510,670)"/>
+    <wire from="(1110,600)" to="(1110,620)"/>
+    <wire from="(1130,150)" to="(1130,160)"/>
+    <wire from="(1130,160)" to="(1500,160)"/>
+    <wire from="(1130,590)" to="(1130,670)"/>
+    <wire from="(1130,590)" to="(1260,590)"/>
+    <wire from="(1150,580)" to="(1150,700)"/>
+    <wire from="(1150,580)" to="(1260,580)"/>
+    <wire from="(1260,530)" to="(1260,560)"/>
+    <wire from="(1260,610)" to="(1260,620)"/>
+    <wire from="(1500,160)" to="(1500,610)"/>
+    <wire from="(160,300)" to="(250,300)"/>
+    <wire from="(230,440)" to="(230,580)"/>
+    <wire from="(230,440)" to="(240,440)"/>
+    <wire from="(250,210)" to="(250,230)"/>
+    <wire from="(250,210)" to="(370,210)"/>
+    <wire from="(250,250)" to="(250,300)"/>
+    <wire from="(250,300)" to="(250,430)"/>
+    <wire from="(250,450)" to="(360,450)"/>
+    <wire from="(260,240)" to="(270,240)"/>
+    <wire from="(270,40)" to="(270,240)"/>
+    <wire from="(360,440)" to="(360,450)"/>
+    <wire from="(360,450)" to="(660,450)"/>
+    <wire from="(370,200)" to="(370,210)"/>
+    <wire from="(370,210)" to="(540,210)"/>
+    <wire from="(440,120)" to="(460,120)"/>
+    <wire from="(440,90)" to="(470,90)"/>
+    <wire from="(460,120)" to="(460,320)"/>
+    <wire from="(460,320)" to="(500,320)"/>
+    <wire from="(460,60)" to="(460,70)"/>
+    <wire from="(460,70)" to="(490,70)"/>
+    <wire from="(470,310)" to="(500,310)"/>
+    <wire from="(470,90)" to="(470,310)"/>
+    <wire from="(490,250)" to="(500,250)"/>
+    <wire from="(490,70)" to="(490,250)"/>
+    <wire from="(510,190)" to="(510,240)"/>
+    <wire from="(510,190)" to="(610,190)"/>
+    <wire from="(510,260)" to="(510,300)"/>
+    <wire from="(510,330)" to="(510,350)"/>
+    <wire from="(510,350)" to="(510,670)"/>
+    <wire from="(510,350)" to="(600,350)"/>
+    <wire from="(510,670)" to="(1130,670)"/>
+    <wire from="(530,310)" to="(540,310)"/>
+    <wire from="(540,210)" to="(540,230)"/>
+    <wire from="(540,210)" to="(640,210)"/>
+    <wire from="(540,250)" to="(540,310)"/>
+    <wire from="(550,40)" to="(550,240)"/>
+    <wire from="(570,390)" to="(660,390)"/>
+    <wire from="(590,550)" to="(590,560)"/>
+    <wire from="(590,550)" to="(640,550)"/>
+    <wire from="(600,100)" to="(600,320)"/>
+    <wire from="(600,320)" to="(620,320)"/>
+    <wire from="(600,350)" to="(600,380)"/>
+    <wire from="(600,350)" to="(630,350)"/>
+    <wire from="(600,380)" to="(750,380)"/>
+    <wire from="(610,190)" to="(1020,190)"/>
+    <wire from="(610,190)" to="(610,310)"/>
+    <wire from="(610,310)" to="(630,310)"/>
+    <wire from="(620,320)" to="(620,330)"/>
+    <wire from="(620,330)" to="(630,330)"/>
+    <wire from="(640,210)" to="(640,220)"/>
+    <wire from="(640,210)" to="(830,210)"/>
+    <wire from="(640,240)" to="(640,250)"/>
+    <wire from="(640,250)" to="(690,250)"/>
+    <wire from="(640,430)" to="(640,550)"/>
+    <wire from="(640,430)" to="(650,430)"/>
+    <wire from="(650,230)" to="(660,230)"/>
+    <wire from="(660,370)" to="(660,390)"/>
+    <wire from="(660,390)" to="(780,390)"/>
+    <wire from="(660,400)" to="(660,420)"/>
+    <wire from="(660,400)" to="(690,400)"/>
+    <wire from="(660,440)" to="(660,450)"/>
+    <wire from="(660,450)" to="(830,450)"/>
+    <wire from="(660,50)" to="(660,230)"/>
+    <wire from="(680,430)" to="(680,620)"/>
+    <wire from="(680,430)" to="(690,430)"/>
+    <wire from="(690,250)" to="(690,310)"/>
+    <wire from="(690,310)" to="(690,400)"/>
+    <wire from="(690,400)" to="(700,400)"/>
+    <wire from="(700,400)" to="(700,420)"/>
+    <wire from="(700,440)" to="(700,560)"/>
+    <wire from="(700,560)" to="(890,560)"/>
+    <wire from="(710,100)" to="(710,320)"/>
+    <wire from="(710,100)" to="(730,100)"/>
+    <wire from="(710,320)" to="(750,320)"/>
+    <wire from="(720,160)" to="(1130,160)"/>
+    <wire from="(720,160)" to="(720,300)"/>
+    <wire from="(720,300)" to="(750,300)"/>
+    <wire from="(730,90)" to="(730,100)"/>
+    <wire from="(740,430)" to="(740,590)"/>
+    <wire from="(740,430)" to="(820,430)"/>
+    <wire from="(740,590)" to="(790,590)"/>
+    <wire from="(750,340)" to="(750,380)"/>
+    <wire from="(780,360)" to="(780,390)"/>
+    <wire from="(790,250)" to="(850,250)"/>
+    <wire from="(790,40)" to="(790,250)"/>
+    <wire from="(790,590)" to="(790,600)"/>
+    <wire from="(810,300)" to="(830,300)"/>
+    <wire from="(830,210)" to="(830,220)"/>
+    <wire from="(830,210)" to="(890,210)"/>
+    <wire from="(830,240)" to="(830,300)"/>
+    <wire from="(830,300)" to="(830,420)"/>
+    <wire from="(830,440)" to="(830,450)"/>
+    <wire from="(830,450)" to="(890,450)"/>
+    <wire from="(840,230)" to="(850,230)"/>
+    <wire from="(850,230)" to="(850,250)"/>
+    <wire from="(890,210)" to="(890,330)"/>
+    <wire from="(890,330)" to="(920,330)"/>
+    <wire from="(890,350)" to="(890,450)"/>
+    <wire from="(890,350)" to="(920,350)"/>
+    <wire from="(890,540)" to="(890,560)"/>
+    <wire from="(890,560)" to="(1260,560)"/>
+    <wire from="(940,310)" to="(940,320)"/>
+    <wire from="(960,340)" to="(1020,340)"/>
+  </circuit>
+  <circuit name="banc_registre">
+    <a name="circuit" val="banc_registre"/>
+    <a name="clabel" val="Banc"/>
+    <a name="clabelfont" val="SansSerif plain 12"/>
+    <a name="clabelup" val="north"/>
+    <a name="simulationFrequency" val="1.0"/>
+    <comp lib="0" loc="(140,210)" name="Constant"/>
+    <comp lib="0" loc="(140,260)" name="Pin">
+      <a name="appearance" val="classic"/>
+      <a name="label" val="NumWriteReg"/>
+      <a name="labelloc" val="north"/>
+      <a name="width" val="2"/>
+    </comp>
+    <comp lib="0" loc="(340,150)" name="Pin">
+      <a name="appearance" val="classic"/>
+      <a name="facing" val="south"/>
+      <a name="label" val="ValueToWrite"/>
+      <a name="labelloc" val="north"/>
+      <a name="width" val="4"/>
+    </comp>
+    <comp lib="0" loc="(370,240)" name="Constant">
+      <a name="value" val="0x0"/>
+      <a name="width" val="4"/>
+    </comp>
+    <comp lib="0" loc="(380,690)" name="Pin">
+      <a name="appearance" val="classic"/>
+      <a name="facing" val="north"/>
+      <a name="label" val="Clock"/>
+    </comp>
+    <comp lib="0" loc="(470,700)" name="Constant">
+      <a name="facing" val="north"/>
+      <a name="value" val="0x0"/>
+    </comp>
+    <comp lib="0" loc="(580,90)" name="Pin">
+      <a name="appearance" val="classic"/>
+      <a name="label" val="NumReadReg"/>
+      <a name="labelloc" val="north"/>
+      <a name="width" val="2"/>
+    </comp>
+    <comp lib="0" loc="(920,380)" name="Pin">
+      <a name="appearance" val="classic"/>
+      <a name="facing" val="west"/>
+      <a name="label" val="ReadValue"/>
+      <a name="labelloc" val="north"/>
+      <a name="type" val="output"/>
+      <a name="width" val="4"/>
+    </comp>
+    <comp lib="2" loc="(210,160)" name="Decoder">
+      <a name="select" val="2"/>
+    </comp>
+    <comp lib="2" loc="(820,290)" name="Multiplexer">
+      <a name="enable" val="true"/>
+      <a name="select" val="2"/>
+      <a name="selloc" val="tr"/>
+      <a name="width" val="4"/>
+    </comp>
+    <comp lib="4" loc="(520,320)" name="Register">
+      <a name="appearance" val="logisim_evolution"/>
+      <a name="width" val="4"/>
+    </comp>
+    <comp lib="4" loc="(530,450)" name="Register">
+      <a name="appearance" val="logisim_evolution"/>
+      <a name="width" val="4"/>
+    </comp>
+    <comp lib="4" loc="(540,580)" name="Register">
+      <a name="appearance" val="logisim_evolution"/>
+      <a name="width" val="4"/>
+    </comp>
+    <wire from="(140,210)" to="(200,210)"/>
+    <wire from="(140,260)" to="(210,260)"/>
+    <wire from="(200,160)" to="(200,210)"/>
+    <wire from="(210,160)" to="(210,260)"/>
+    <wire from="(230,120)" to="(300,120)"/>
+    <wire from="(230,130)" to="(280,130)"/>
+    <wire from="(230,140)" to="(270,140)"/>
+    <wire from="(230,150)" to="(260,150)"/>
+    <wire from="(260,150)" to="(260,480)"/>
+    <wire from="(260,480)" to="(430,480)"/>
+    <wire from="(270,140)" to="(270,420)"/>
+    <wire from="(270,420)" to="(460,420)"/>
+    <wire from="(280,130)" to="(280,360)"/>
+    <wire from="(280,360)" to="(520,360)"/>
+    <wire from="(300,120)" to="(300,300)"/>
+    <wire from="(300,300)" to="(420,300)"/>
+    <wire from="(320,160)" to="(320,350)"/>
+    <wire from="(320,160)" to="(340,160)"/>
+    <wire from="(320,350)" to="(320,410)"/>
+    <wire from="(320,350)" to="(520,350)"/>
+    <wire from="(320,410)" to="(320,470)"/>
+    <wire from="(320,410)" to="(480,410)"/>
+    <wire from="(320,470)" to="(450,470)"/>
+    <wire from="(340,150)" to="(340,160)"/>
+    <wire from="(370,240)" to="(370,270)"/>
+    <wire from="(370,270)" to="(780,270)"/>
+    <wire from="(380,390)" to="(380,520)"/>
+    <wire from="(380,390)" to="(520,390)"/>
+    <wire from="(380,520)" to="(380,650)"/>
+    <wire from="(380,520)" to="(530,520)"/>
+    <wire from="(380,650)" to="(380,690)"/>
+    <wire from="(380,650)" to="(540,650)"/>
+    <wire from="(420,430)" to="(420,540)"/>
+    <wire from="(420,430)" to="(550,430)"/>
+    <wire from="(420,540)" to="(420,670)"/>
+    <wire from="(420,540)" to="(560,540)"/>
+    <wire from="(420,670)" to="(470,670)"/>
+    <wire from="(430,480)" to="(430,630)"/>
+    <wire from="(430,630)" to="(540,630)"/>
+    <wire from="(450,470)" to="(450,610)"/>
+    <wire from="(450,610)" to="(540,610)"/>
+    <wire from="(460,420)" to="(460,500)"/>
+    <wire from="(460,500)" to="(530,500)"/>
+    <wire from="(470,670)" to="(470,700)"/>
+    <wire from="(470,670)" to="(570,670)"/>
+    <wire from="(480,410)" to="(480,480)"/>
+    <wire from="(480,480)" to="(530,480)"/>
+    <wire from="(520,360)" to="(520,370)"/>
+    <wire from="(550,410)" to="(550,430)"/>
+    <wire from="(580,350)" to="(590,350)"/>
+    <wire from="(580,90)" to="(590,90)"/>
+    <wire from="(590,120)" to="(640,120)"/>
+    <wire from="(590,280)" to="(590,350)"/>
+    <wire from="(590,280)" to="(780,280)"/>
+    <wire from="(590,480)" to="(640,480)"/>
+    <wire from="(590,90)" to="(590,120)"/>
+    <wire from="(600,610)" to="(770,610)"/>
+    <wire from="(640,120)" to="(640,230)"/>
+    <wire from="(640,230)" to="(800,230)"/>
+    <wire from="(640,290)" to="(640,480)"/>
+    <wire from="(640,290)" to="(780,290)"/>
+    <wire from="(770,300)" to="(770,610)"/>
+    <wire from="(770,300)" to="(780,300)"/>
+    <wire from="(800,230)" to="(800,270)"/>
+    <wire from="(820,290)" to="(830,290)"/>
+    <wire from="(830,290)" to="(830,310)"/>
+    <wire from="(830,310)" to="(910,310)"/>
+    <wire from="(910,310)" to="(910,380)"/>
+    <wire from="(910,380)" to="(920,380)"/>
+  </circuit>
+</project>
diff --git a/semestre 3/architecture des ordinateurs/tme/tme11/pgcd_ne_fonctionnant_pas.circ b/semestre 3/architecture des ordinateurs/tme/tme11/pgcd_ne_fonctionnant_pas.circ
new file mode 100644
index 0000000..70598c7
--- /dev/null
+++ b/semestre 3/architecture des ordinateurs/tme/tme11/pgcd_ne_fonctionnant_pas.circ
@@ -0,0 +1,344 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<project source="4.0.0" version="1.0">
+  This file is intended to be loaded by Logisim-evolution v4.0.0(https://github.com/logisim-evolution/).
+
+  <lib desc="#Wiring" name="0">
+    <tool name="Pin">
+      <a name="appearance" val="classic"/>
+    </tool>
+  </lib>
+  <lib desc="#Gates" name="1"/>
+  <lib desc="#Plexers" name="2"/>
+  <lib desc="#Arithmetic" name="3"/>
+  <lib desc="#Memory" name="4"/>
+  <lib desc="#I/O" name="5"/>
+  <lib desc="#TTL" name="6"/>
+  <lib desc="#TCL" name="7"/>
+  <lib desc="#Base" name="8"/>
+  <lib desc="#BFH-Praktika" name="9"/>
+  <lib desc="#Input/Output-Extra" name="10"/>
+  <lib desc="#Soc" name="11"/>
+  <main name="main"/>
+  <options>
+    <a name="gateUndefined" val="ignore"/>
+    <a name="simlimit" val="1000"/>
+    <a name="simrand" val="0"/>
+  </options>
+  <mappings>
+    <tool lib="8" map="Button2" name="Poke Tool"/>
+    <tool lib="8" map="Button3" name="Menu Tool"/>
+    <tool lib="8" map="Ctrl Button1" name="Menu Tool"/>
+  </mappings>
+  <toolbar>
+    <tool lib="8" name="Poke Tool"/>
+    <tool lib="8" name="Edit Tool"/>
+    <tool lib="8" name="Wiring Tool"/>
+    <tool lib="8" name="Text Tool"/>
+    <sep/>
+    <tool lib="0" name="Pin"/>
+    <tool lib="0" name="Pin">
+      <a name="facing" val="west"/>
+      <a name="type" val="output"/>
+    </tool>
+    <sep/>
+    <tool lib="1" name="NOT Gate"/>
+    <tool lib="1" name="AND Gate"/>
+    <tool lib="1" name="OR Gate"/>
+    <tool lib="1" name="XOR Gate"/>
+    <tool lib="1" name="NAND Gate"/>
+    <tool lib="1" name="NOR Gate"/>
+    <sep/>
+    <tool lib="4" name="D Flip-Flop"/>
+    <tool lib="4" name="Register"/>
+  </toolbar>
+  <circuit name="main">
+    <a name="appearance" val="logisim_evolution"/>
+    <a name="circuit" val="main"/>
+    <a name="circuitnamedboxfixedsize" val="true"/>
+    <a name="clabelfont" val="SansSerif bold 14"/>
+    <a name="simulationFrequency" val="1.0"/>
+    <comp lib="0" loc="(260,590)" name="Pin">
+      <a name="appearance" val="NewPins"/>
+      <a name="width" val="4"/>
+    </comp>
+    <comp lib="0" loc="(260,730)" name="Pin">
+      <a name="appearance" val="NewPins"/>
+      <a name="width" val="4"/>
+    </comp>
+    <comp lib="0" loc="(370,700)" name="Clock">
+      <a name="appearance" val="NewPins"/>
+    </comp>
+    <comp lib="0" loc="(420,510)" name="Probe">
+      <a name="appearance" val="NewPins"/>
+    </comp>
+    <comp lib="0" loc="(490,1000)" name="Constant"/>
+    <comp lib="1" loc="(220,1250)" name="NOT Gate"/>
+    <comp lib="1" loc="(230,1220)" name="NOT Gate"/>
+    <comp lib="1" loc="(260,1210)" name="NOT Gate"/>
+    <comp lib="1" loc="(280,1140)" name="NOT Gate"/>
+    <comp lib="1" loc="(280,950)" name="NOT Gate"/>
+    <comp lib="1" loc="(280,970)" name="NOT Gate"/>
+    <comp lib="1" loc="(290,1090)" name="NOT Gate"/>
+    <comp lib="1" loc="(290,1110)" name="NOT Gate"/>
+    <comp lib="1" loc="(330,1230)" name="AND Gate">
+      <a name="inputs" val="4"/>
+    </comp>
+    <comp lib="1" loc="(360,970)" name="AND Gate">
+      <a name="inputs" val="4"/>
+    </comp>
+    <comp lib="1" loc="(390,1110)" name="AND Gate">
+      <a name="inputs" val="4"/>
+    </comp>
+    <comp lib="1" loc="(430,1250)" name="NOR Gate"/>
+    <comp lib="1" loc="(480,950)" name="OR Gate"/>
+    <comp lib="1" loc="(530,790)" name="OR Gate">
+      <a name="facing" val="west"/>
+    </comp>
+    <comp lib="1" loc="(700,910)" name="NOT Gate">
+      <a name="facing" val="north"/>
+    </comp>
+    <comp lib="1" loc="(720,860)" name="AND Gate">
+      <a name="facing" val="north"/>
+      <a name="inputs" val="3"/>
+      <a name="label" val="init"/>
+    </comp>
+    <comp lib="1" loc="(720,910)" name="NOT Gate">
+      <a name="facing" val="north"/>
+    </comp>
+    <comp lib="1" loc="(790,910)" name="NOT Gate">
+      <a name="facing" val="north"/>
+    </comp>
+    <comp lib="1" loc="(810,860)" name="AND Gate">
+      <a name="facing" val="north"/>
+      <a name="inputs" val="3"/>
+      <a name="label" val="S1"/>
+    </comp>
+    <comp lib="1" loc="(830,910)" name="NOT Gate">
+      <a name="facing" val="north"/>
+    </comp>
+    <comp lib="1" loc="(890,910)" name="NOT Gate">
+      <a name="facing" val="north"/>
+    </comp>
+    <comp lib="1" loc="(910,860)" name="AND Gate">
+      <a name="facing" val="north"/>
+      <a name="inputs" val="3"/>
+      <a name="label" val="S2"/>
+    </comp>
+    <comp lib="1" loc="(980,810)" name="OR Gate"/>
+    <comp lib="2" loc="(460,580)" name="Multiplexer">
+      <a name="width" val="4"/>
+    </comp>
+    <comp lib="2" loc="(460,700)" name="Multiplexer">
+      <a name="width" val="4"/>
+    </comp>
+    <comp lib="2" loc="(730,590)" name="Multiplexer">
+      <a name="width" val="4"/>
+    </comp>
+    <comp lib="2" loc="(740,700)" name="Multiplexer">
+      <a name="width" val="4"/>
+    </comp>
+    <comp lib="3" loc="(100,880)" name="Comparator">
+      <a name="width" val="4"/>
+    </comp>
+    <comp lib="3" loc="(850,640)" name="Subtractor">
+      <a name="width" val="4"/>
+    </comp>
+    <comp lib="4" loc="(530,1080)" name="Register">
+      <a name="appearance" val="logisim_evolution"/>
+      <a name="label" val="C1"/>
+      <a name="width" val="1"/>
+    </comp>
+    <comp lib="4" loc="(530,1250)" name="Register">
+      <a name="appearance" val="logisim_evolution"/>
+      <a name="label" val="C0"/>
+      <a name="width" val="1"/>
+    </comp>
+    <comp lib="4" loc="(530,920)" name="Register">
+      <a name="appearance" val="logisim_evolution"/>
+      <a name="label" val="C2"/>
+      <a name="width" val="1"/>
+    </comp>
+    <comp lib="4" loc="(590,550)" name="Register">
+      <a name="appearance" val="logisim_evolution"/>
+      <a name="label" val="a"/>
+      <a name="width" val="4"/>
+    </comp>
+    <comp lib="4" loc="(590,670)" name="Register">
+      <a name="appearance" val="logisim_evolution"/>
+      <a name="label" val="b"/>
+      <a name="width" val="4"/>
+    </comp>
+    <wire from="(100,870)" to="(130,870)"/>
+    <wire from="(100,880)" to="(140,880)"/>
+    <wire from="(1000,760)" to="(1000,810)"/>
+    <wire from="(130,1250)" to="(190,1250)"/>
+    <wire from="(130,870)" to="(130,1250)"/>
+    <wire from="(140,1140)" to="(250,1140)"/>
+    <wire from="(140,880)" to="(140,990)"/>
+    <wire from="(140,990)" to="(140,1140)"/>
+    <wire from="(140,990)" to="(310,990)"/>
+    <wire from="(150,1210)" to="(150,1270)"/>
+    <wire from="(150,1210)" to="(220,1210)"/>
+    <wire from="(150,1270)" to="(370,1270)"/>
+    <wire from="(160,1120)" to="(160,1240)"/>
+    <wire from="(160,1120)" to="(340,1120)"/>
+    <wire from="(160,1240)" to="(280,1240)"/>
+    <wire from="(160,850)" to="(160,980)"/>
+    <wire from="(160,850)" to="(620,850)"/>
+    <wire from="(160,980)" to="(160,1120)"/>
+    <wire from="(160,980)" to="(310,980)"/>
+    <wire from="(190,1110)" to="(190,1220)"/>
+    <wire from="(190,1110)" to="(260,1110)"/>
+    <wire from="(190,1220)" to="(200,1220)"/>
+    <wire from="(190,860)" to="(190,970)"/>
+    <wire from="(190,860)" to="(610,860)"/>
+    <wire from="(190,970)" to="(190,1110)"/>
+    <wire from="(190,970)" to="(250,970)"/>
+    <wire from="(220,1090)" to="(220,1210)"/>
+    <wire from="(220,1090)" to="(260,1090)"/>
+    <wire from="(220,1210)" to="(230,1210)"/>
+    <wire from="(220,1250)" to="(280,1250)"/>
+    <wire from="(220,870)" to="(220,950)"/>
+    <wire from="(220,870)" to="(420,870)"/>
+    <wire from="(220,950)" to="(220,1090)"/>
+    <wire from="(220,950)" to="(250,950)"/>
+    <wire from="(230,1220)" to="(280,1220)"/>
+    <wire from="(260,1210)" to="(280,1210)"/>
+    <wire from="(260,590)" to="(430,590)"/>
+    <wire from="(260,730)" to="(380,730)"/>
+    <wire from="(280,1140)" to="(340,1140)"/>
+    <wire from="(280,950)" to="(310,950)"/>
+    <wire from="(280,970)" to="(290,970)"/>
+    <wire from="(290,1090)" to="(340,1090)"/>
+    <wire from="(290,1110)" to="(310,1110)"/>
+    <wire from="(290,960)" to="(290,970)"/>
+    <wire from="(290,960)" to="(310,960)"/>
+    <wire from="(30,530)" to="(30,890)"/>
+    <wire from="(30,530)" to="(660,530)"/>
+    <wire from="(30,890)" to="(60,890)"/>
+    <wire from="(310,1100)" to="(310,1110)"/>
+    <wire from="(310,1100)" to="(340,1100)"/>
+    <wire from="(330,1230)" to="(370,1230)"/>
+    <wire from="(340,1130)" to="(340,1140)"/>
+    <wire from="(360,970)" to="(430,970)"/>
+    <wire from="(370,1050)" to="(450,1050)"/>
+    <wire from="(370,700)" to="(370,750)"/>
+    <wire from="(370,750)" to="(370,1050)"/>
+    <wire from="(370,750)" to="(560,750)"/>
+    <wire from="(380,710)" to="(380,730)"/>
+    <wire from="(380,710)" to="(430,710)"/>
+    <wire from="(390,1110)" to="(530,1110)"/>
+    <wire from="(40,670)" to="(40,870)"/>
+    <wire from="(40,670)" to="(650,670)"/>
+    <wire from="(40,870)" to="(60,870)"/>
+    <wire from="(400,610)" to="(400,730)"/>
+    <wire from="(400,610)" to="(440,610)"/>
+    <wire from="(400,730)" to="(440,730)"/>
+    <wire from="(420,490)" to="(420,510)"/>
+    <wire from="(420,490)" to="(890,490)"/>
+    <wire from="(420,510)" to="(420,570)"/>
+    <wire from="(420,570)" to="(420,690)"/>
+    <wire from="(420,570)" to="(430,570)"/>
+    <wire from="(420,690)" to="(430,690)"/>
+    <wire from="(420,870)" to="(420,930)"/>
+    <wire from="(420,870)" to="(590,870)"/>
+    <wire from="(420,930)" to="(430,930)"/>
+    <wire from="(430,1250)" to="(530,1250)"/>
+    <wire from="(440,600)" to="(440,610)"/>
+    <wire from="(440,720)" to="(440,730)"/>
+    <wire from="(440,730)" to="(440,830)"/>
+    <wire from="(440,830)" to="(600,830)"/>
+    <wire from="(450,1050)" to="(450,1150)"/>
+    <wire from="(450,1150)" to="(450,1320)"/>
+    <wire from="(450,1150)" to="(530,1150)"/>
+    <wire from="(450,1320)" to="(530,1320)"/>
+    <wire from="(450,990)" to="(450,1050)"/>
+    <wire from="(450,990)" to="(530,990)"/>
+    <wire from="(460,580)" to="(590,580)"/>
+    <wire from="(460,700)" to="(590,700)"/>
+    <wire from="(480,950)" to="(530,950)"/>
+    <wire from="(490,1000)" to="(490,1130)"/>
+    <wire from="(490,1130)" to="(490,1300)"/>
+    <wire from="(490,1130)" to="(530,1130)"/>
+    <wire from="(490,1300)" to="(530,1300)"/>
+    <wire from="(490,520)" to="(490,600)"/>
+    <wire from="(490,520)" to="(940,520)"/>
+    <wire from="(490,600)" to="(590,600)"/>
+    <wire from="(490,970)" to="(490,1000)"/>
+    <wire from="(490,970)" to="(530,970)"/>
+    <wire from="(520,720)" to="(520,790)"/>
+    <wire from="(520,720)" to="(590,720)"/>
+    <wire from="(520,790)" to="(530,790)"/>
+    <wire from="(530,1250)" to="(530,1280)"/>
+    <wire from="(560,620)" to="(560,750)"/>
+    <wire from="(560,620)" to="(590,620)"/>
+    <wire from="(560,750)" to="(590,750)"/>
+    <wire from="(580,770)" to="(770,770)"/>
+    <wire from="(580,810)" to="(600,810)"/>
+    <wire from="(590,1110)" to="(610,1110)"/>
+    <wire from="(590,1280)" to="(620,1280)"/>
+    <wire from="(590,740)" to="(590,750)"/>
+    <wire from="(590,870)" to="(590,950)"/>
+    <wire from="(590,950)" to="(700,950)"/>
+    <wire from="(600,810)" to="(600,830)"/>
+    <wire from="(600,830)" to="(720,830)"/>
+    <wire from="(610,1060)" to="(610,1110)"/>
+    <wire from="(610,1060)" to="(720,1060)"/>
+    <wire from="(610,860)" to="(610,1060)"/>
+    <wire from="(620,1280)" to="(740,1280)"/>
+    <wire from="(620,850)" to="(620,1280)"/>
+    <wire from="(650,580)" to="(660,580)"/>
+    <wire from="(650,670)" to="(650,690)"/>
+    <wire from="(650,690)" to="(650,700)"/>
+    <wire from="(650,690)" to="(680,690)"/>
+    <wire from="(660,530)" to="(660,580)"/>
+    <wire from="(660,580)" to="(670,580)"/>
+    <wire from="(670,580)" to="(670,710)"/>
+    <wire from="(670,580)" to="(700,580)"/>
+    <wire from="(670,710)" to="(710,710)"/>
+    <wire from="(680,600)" to="(680,690)"/>
+    <wire from="(680,600)" to="(700,600)"/>
+    <wire from="(680,690)" to="(710,690)"/>
+    <wire from="(700,940)" to="(700,950)"/>
+    <wire from="(700,950)" to="(790,950)"/>
+    <wire from="(710,610)" to="(760,610)"/>
+    <wire from="(720,1060)" to="(810,1060)"/>
+    <wire from="(720,720)" to="(760,720)"/>
+    <wire from="(720,830)" to="(720,860)"/>
+    <wire from="(720,830)" to="(870,830)"/>
+    <wire from="(720,940)" to="(720,1060)"/>
+    <wire from="(730,590)" to="(790,590)"/>
+    <wire from="(740,1070)" to="(740,1280)"/>
+    <wire from="(740,1070)" to="(830,1070)"/>
+    <wire from="(740,700)" to="(790,700)"/>
+    <wire from="(740,910)" to="(740,1070)"/>
+    <wire from="(760,610)" to="(760,720)"/>
+    <wire from="(760,720)" to="(810,720)"/>
+    <wire from="(770,770)" to="(770,780)"/>
+    <wire from="(770,780)" to="(810,780)"/>
+    <wire from="(790,590)" to="(790,630)"/>
+    <wire from="(790,630)" to="(810,630)"/>
+    <wire from="(790,650)" to="(790,700)"/>
+    <wire from="(790,650)" to="(810,650)"/>
+    <wire from="(790,940)" to="(790,950)"/>
+    <wire from="(790,950)" to="(890,950)"/>
+    <wire from="(810,1060)" to="(910,1060)"/>
+    <wire from="(810,720)" to="(810,780)"/>
+    <wire from="(810,780)" to="(810,860)"/>
+    <wire from="(810,910)" to="(810,1060)"/>
+    <wire from="(830,1070)" to="(930,1070)"/>
+    <wire from="(830,940)" to="(830,1070)"/>
+    <wire from="(850,640)" to="(890,640)"/>
+    <wire from="(870,790)" to="(870,830)"/>
+    <wire from="(870,790)" to="(930,790)"/>
+    <wire from="(890,490)" to="(890,640)"/>
+    <wire from="(890,940)" to="(890,950)"/>
+    <wire from="(910,830)" to="(910,860)"/>
+    <wire from="(910,830)" to="(930,830)"/>
+    <wire from="(910,910)" to="(910,1060)"/>
+    <wire from="(930,910)" to="(930,1070)"/>
+    <wire from="(940,520)" to="(940,760)"/>
+    <wire from="(940,760)" to="(1000,760)"/>
+    <wire from="(980,810)" to="(1000,810)"/>
+  </circuit>
+</project>